Description

General Electric DS200DENQF1BDB module

General Electric DS200DENQF1BDB Automation Communication Module
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Design and Implementation of CPCI Data Bus Interface

CPCI bus is the current popular high-speed embedded computer bus. At present, most of the interfaces of embedded computer systems will eventually interact with computer memory through CPCI bus. The bus specification of CPCI ensures its good compatibility and reliability.

The system designed in this paper uses the CPCI protocol conversion chip PCI9054 produced by PLX company, and generates corresponding control signals in FPGA through Verilog HDL language to complete the fast reading and writing of data, thus realizing high-speed data communication with CPCI bus.

1 System design General Electric DS200DENQF1BDB

The system is mainly composed of PCI9054 and FPGA. The system structure diagram and signal connection are shown in Figure 1. By using the programmability of FPGA, more extended functions can be realized, such as indirect high-speed communication with DSP, A/D and other different rates. The function of the protocol conversion chip PCI9054 is to ensure that the data between the local data acquisition board and the main CPU board can be transmitted quickly and accurately.

2 PCI9054 performance analysis

PCI9054 is a general interface chip based on PCI V2.2 bus specification produced by PLX Company. It supports single byte mode and burst mode. Its bus end supports 32-bit/33 MHz transmission, and the local end can reach the maximum transmission rate of 132 Mbit · s-1 through burst mode, and can control and change the bus width of the local end.

PCI9054 can be seen as a bridge between CPCI bus and local user local bus. Because PCI9054 has six programmable FIFO memories for data caching, so as to ensure the correctness and real-time of data transmission between them. In addition, PCI9054 allows either end to control the bus as the master device, and the other end to respond to the bus as the target device.

PCI9054 has a number of register groups inside to control the working status and working mode of its two ends. PCI9054 performs unified address mapping for all register groups and FIFOs in it. Users can access all FIFOs and each byte of register groups through programming from both ends to view the working status of both ends and change the working mode of both ends.

3 Interface design of PCI9054 local bus

The design idea of the whole CPCI interface is as follows: FPGA is connected to the CPCI bus through the bridge chip PCI9054, and its internal uses asynchronous dual-port RAM to buffer high-speed data. The asynchronous dual-port RAM in FPGA is controlled by using Verilog HDL language programming to realize high-speed transmission of system data between the embedded CUP board memory and the CPCI board.

PCI9054 provides three physical bus interfaces: CPCI bus interface, LOCAL bus interface and serial EPROM interface. The driver package of the CPCI bus interface protocol in the embedded operating system has been included, and the initialization of the serial EEPROM is written online by PLX”s PLXMON software in the embedded operating system. Therefore, the focus of the system design is on the control and transmission of the local bus interface. The interface circuit diagram is shown in Figure 2.

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Company advantage service:
1.Has been engaged in industrial control industry for a long time, with a large number of inventories.
2.Industry leading, price advantage, quality assurance
3.Diversified models and products, and all kinds of rare and discontinued products
4.15 days free replacement for quality problems

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General Electric DS200DENQF1BDB

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